A synchronous semiconductor storage device as represented by a synchronous DRAM (Synchronous Dynamic Random Access Memory) is widely used for a main memory and the like of a personal computer. Because the synchronous semiconductor storage device can input and output data in synchronism with a clock signal supplied from a controller, a data transfer rate of the data can be increased by using a higher-speed clock.
However, so long as a DRAM core performs an analog operation in the synchronous DRAM, a considerably weak charge needs to be amplified based on a sense operation. Therefore, the semiconductor storage device cannot shorten the time from when a first read command is issued until when first data is output. The semiconductor device can output the first data in synchronism with an external clock after a lapse of a predetermined delay time since the issuance of the read command. This delay time is generally called “CAS latency” and is set to an integer times a clock cycle. For example, when the CAS latency is 5 (CL=5), the semiconductor storage device outputs the first data in synchronism with the external clock after five cycles since the device reads the read command synchronously with the external clock. In other words, the semiconductor device outputs the first data after a lapse of the five clocks.
However, a peripheral circuit part of the synchronous DRAM performs an operation in synchronism with various kinds of internal clocks different from the external clock. Therefore, in order to correctly output the first data in synchronism with the external clock after taking in the read command, the semiconductor storage device needs to use an “output control signal generating circuit” that synchronizes an internal command synchronous with the internal clock with the external clock.
FIG. 3 is a circuit diagram of a conventional output control signal generating circuit.
The output control signal generating circuit shown in FIG. 3 is the one that sets the CAS latency to 5 (CL=5) and includes four (the number of CL−1) latch circuits 11 to 14 that are connected in cascade. Each of these latch circuits 11 to 14 is what is called a D latch circuit that includes an input terminal D, an output terminal Q, and a clock terminal C. Each D latch circuit takes in a signal supplied to the input terminal D, in response to a change of a signal supplied to the clock terminal C from a low level to a high level, and outputs the signal supplied to the input terminal D, from the output terminal Q.
An internal clock PCLK is supplied in common to the clock terminal C of each of the first to the third latch circuits 11 to 13 out of the four latch circuits 11 to 14. On the other hand, an internal clock LCLKD that is an internal clock LCLK delayed by a delay circuit 19 is supplied to the clock terminal C of the last latch circuit 14. An internal command R(0) is supplied to the input terminal D of the first latch circuit 11, and this internal command R(0) is sequentially shifted to the latch circuits 12 to 14. The (0) attached to the end of the internal command R means an internal command that is linked to an active edge #0 of an external clock CK. Therefore, internal commands R that are linked to active edges #1 to #3 of the external clock CK are expressed as internal commands R(1) to R(3) respectively.
The last latch circuit 14 takes in the internal command R(3) and outputs this internal command as an output control signal DR(4) as one kind of the internal command. Therefore, the output control signal DR(4) is synchronism with an active edge #4 of the external clock CK.
FIG. 4 is a schematic diagram of a circuit that generates the internal clocks PCLK and LCLK.
As shown in FIG. 4, the internal clocks PCLK and LCLK are generated based on the external clock CK. In other words, an input buffer 21 buffers the external clock CK and supplies the buffered external clock CK to an internal buffer 22 and a DLL (Delay Locked Loop) circuit 23, respectively. The clock that passes the internal buffer 22 becomes the internal clock PCLK, and the clock that is generated by the DLL circuit 23 becomes the internal clock LCLK. Consequently, the internal clock PCLK is delayed by the input buffer 21 and the internal buffer 22, and becomes a signal of which phase is delayed from the phase of the external clock CK. On the other hand, the internal clock LCLK becomes a signal of which phase is advanced from that of the external clock CK, due to the function of the DLL circuit 23.
The operation of the output control signal generating circuit shown in FIG. 3 is explained next.
FIG. 5 is a timing diagram indicating the operation of the output control signal generating circuit shown in FIG. 3.
As shown in FIG. 5, when a read command READ as one kind of the external command is issued in synchronously with the active edge #0 of the external clock CK, the internal command R(0) is generated based on this taking in of the read command READ. A predetermined delay time td0 is necessary before the internal command R(0) is generated after the read command READ is issued. Therefore, the internal command R(0) is generated after the delay time td0, from the active edge #0 of the external clock CK. As explained above, the internal command R(0) is generated at the timing linked to the active edge #0 of the external clock CK.
The internal command R(0) generated in this way is supplied to the latch circuit 11 within the output control signal generating circuit, as shown in FIG. 3. As described above, the internal clock PCLK is supplied in common to the clock terminal C of each of the latch circuits 11 to 13. Consequently, the latch circuit 11 takes in the internal command R(0) in synchronism with the internal clock PCLK. Thereafter, the internal command R(0) is shifted sequentially.
More specifically, the latch circuit 11 latches the internal command R(0) in synchronism with the active edge #1 of the internal clock PCLK and generates the internal command R(1). In this case the active edge #1 of the internal clock PCLK is the edge corresponding to the active edge #1 of the external clock CK. Similarly, the latch circuit 12 latches the internal command R(1) in synchronism with the active edge #2 of the internal clock PCLK and generates the internal command R(2). Further, the latch circuit 13 latches the internal command R(2) in synchronism with the active edge #3 of the internal clock PCLK and generates the internal command R(3).
As shown in FIG. 5, the internal clock PCLK is a signal of which phase is delayed from that of the external clock CK by td1. Therefore, a latch margin M1 for the latch circuit 11 to take in the internal command R(0) is expressed asM1=tCK−td0+td1  (1),where tCK represents the cycle of the external clock CK. On the other hand, latch margins M2 and M3 of the latch circuits 12 and 13 are equal to tCK, respectively.
At the time of generating the output control signal DR(4) from the internal command R(3), clocks are changed. In other words, the latch circuit 13 that generates the internal command R(3) operates synchronously with the internal clock PCLK. On the other hand, the latch circuit 14 that generates the output control signal DR(4) operates synchronously with the internal clock LCLKD. Therefore, a latch margin M4 for the latch circuit 14 to take in the internal command R(3) is different from the latch margins M2 and M3.
In other words, as shown in FIG. 5, the phase of the internal clock LCLK is advanced from that of the external clock CK by td2 (the phase is delayed by −td2), and the phase of the internal clock LCLKD is delayed from that of the internal clock LCLK by td3. Therefore, a latch margin M4 (a change margin) for the latch circuit 14 to take in the internal command R3 is expressed asM4=tCK−td1−td2+td3  (2).
The output control signal DR(4) that is output from the latch circuit 14 is supplied to an output buffer not shown. The output buffer starts the output operation of the data in synchronism with an active edge #5 of the internal clock LCLK. In this case, the output buffer has an operation delay that is the same as the delay of the above td2. As a result, the data is actually output synchronously with the active edge #5 of the external clock CK.
Based on the above operation, the output control circuit signal generating circuit shown in FIG. 3 can generate the output control signal DR(4) so that the CAS latency becomes 5 (CL=5) and supply this output control signal DR(4) to the output buffer.
However, according to the output control signal generating circuit shown in FIG. 3, while the generation timing of the internal command R(0) is linked to the active edge #0 of the external clock CK, the circuit uses the signal linked to the active edge #1 of the external clock CK (the active edge #1 of the internal clock PCLK) at the time of taking in the internal command R(0). Therefore, as is clear from the above expression (1), the latch margin M1 depends on the cycle tCK of the external clock CK. Consequently, when the frequency of the external clock CK becomes high, there is risk that the latch margin M1 becomes short and the output control becomes difficult.
Further, at the time of generating the output control signal DR(4) from the internal command R(3), clocks need to be changed. Consequently, there is also a risk that the latch margin M4 as a change margin becomes short.
In order to avoid the need for the change of clocks, it is considered suitable to use the internal clock LCLK of which phase is advanced from the phase of the external clock CK, in all the latch circuits including the first latch circuit, without using the internal clock PCLK of which phase is delayed from the phase of the external clock CK, as described in Japanese Patent Laid Open No. 2003-281888. However, according to the system described in the Japanese Patent Laid Open No. 2003-281888, a signal linked to the active edge #1 of the external clock CK (the active edge #1 of the internal clock LCLK) is also used to take in the internal command R(0). Therefore, the latch margin M1 depends on the cycle tCK of the external clock, in a similar manner to that of the output control signal generating circuit shown in FIG. 3. Consequently, when the frequency of the external clock CK becomes high, there is a risk that the output control becomes difficult.
It is clear from the circuit configuration described in the Japanese Patent Laid Open No. 2003-281888 that the latch margin M1 depends on the cycle tCK of the external clock. For example, in the Japanese Patent Laid Open No. 2003-281888, when it is assumed that the CAS latency is 5, four latch circuits connected in series are required to generate an output control signal LATENCY in response to a read master signal RM being activated. In other words, the number of latch circuits becomes smaller than the number of the CAS latency by one. The latch margin of the read master signal RM depends on a difference between PLCKDQ that is phase-controlled by a delay synchronous loop circuit and the external clock. In other words, the latch margin depends on a time component proportional to the external clock cycle tCK. When the CAS latency takes other value, it is also clear that the latch margin of the read master signal RM depends on the external clock cycle.